Memory in all forms is an integral part of computing, but it also consumes plenty of the power budget at both the chip and system level while also being a limiting factor for performance.

Intel also conducted the world's first functional demonstration of 3D-stacked ferroelectric memory. The most impressive aspect of this tech is that ferroelectric trench capacitors can be stacked vertically on the logic die atop the transistors. That enables layering the memory atop the logic elements instead of being in its own distinct region, as we see with other types of embedded memory, like SRAM used for L1 and L2 caches.

Ferroelectric memory also enables a similar capability to what we see with NAND flash — the ability to store multiple bits of data in a structure that would typically only store one bit. In this case, Intel demonstrated the ability to store four bits per trench.

Naturally, this approach would increase both bandwidth and memory density while reducing latency, yielding much larger and much faster on-chip caches.

In the same vein as the electrical contacts modeling for 2D structures, Intel also shared its modeling efforts for mixed phases and defects for ferroelectric hafnia devices, which will, in turn, further the company's own research and development processes.

Intel is also researching transistors that 'don't forget,' meaning they don't lose their data (on/off state) when they lose power. This is akin to any non-volatile storage, like NAND, that can retain its state when power is removed, but it comes in the form of a logic transistor. Intel says it has hurdled two of the three roadblocks to using this technology at room temperature. We're particularly looking forward to this presentation.

Intel's other papers at the event outline other research areas, like GaN-on-silicon wafers that can enable future technologies beyond 5G, and better ways to store quantum information to create better qubits for quantum computing.

It's been 75 years since the transistor altered the course of history, and Intel's Dr. Ann Kelleher, the VP and GM of Technology Development, will also give a special address at IEDM on Monday. The "Celebrating 75 Years of the Transistor! A Look at the Evolution of Moore’s Law Innovation" presentation takes place at 9:45 am PT on Monday, December 5. We'll follow up with coverage of that presentation soon.