As you can see in the image of the Alder Lake die above, the hybrid architecture pairs a 3MB slice of L3 cache (labeled as LLC) next to each 'block' of cores. The P-cores, in dark blue, each have an L3 slice nearby, while the E-cores, in light blue, come in quad-core clusters that also have a 3MB slice of L3 cache nearby. These slices of cache are shared among all cores.

The new Raptor Lake 8+ 16 die (covered in the previous section) comes with 16 E-Cores. Those additional E-Cores would equate to the above Alder Lake die being stretched to accommodate two more light blue quad-core clusters of E-Cores. Those two clusters would come with two more 3MB L3 cache slices, bringing the total capacity to the 36MB we see with the Core i9-13900K.

Interestingly, Alder Lake's cache scheme introduced a new way for Intel to disable cache for lower core count SKUs. In the past, to create lower-end SKUs with fewer cores, Intel disabled entire slices of L3 cache (the LLC blocks in the image) in lockstep with any cores it disabled. With Alder Lake, Intel transitioned to not disabling any entire slice of L3, instead merely disabling some banks in each slice, thus reducing per-slice capacity (from 3MB to 2MB, for instance). This makes plenty of sense as it keeps stops on the ring bus active, and it also allows for creating SKUs with higher cache capacity than we would typically expect based on the number of disabled cores.

As such, we can't simply guess the amount of L3 cache per Raptor Lake chip based on the core count alone. Instead, we'll have to wait to see more detailed information. For now, we simply have confirmation that the Core i9-13900K and Core i9-13900 will come with 36MB of total L3 cache. However, Intel's new L3 cache policy leaves room for cache capacity improvements on all SKUs that leverage the 8+16 die.

Intel has increased per-core L2 cache capacity for both the P-Cores and the E-Cores. The E-Cores see an increase to 2MB of private L2 cache per core, a 60% increase over the 1.25 MB per core found in Alder Lake. Intel also boosted the amount of L2 cache shared among each quad-core cluster of E-Cores to 4 MB, a doubling over the 2MB with Alder Lake. That means we'll see up to 32MB of L2 cache. As we've seen with Intel's previous chips that got a big increase in L2 capacity, this type of improvement tends to result in better performance in multi-threaded workloads, but it is possible that it could result in higher IPC in some workloads due to keeping the cores fed with more data. It should also help free the ring from some traffic that would otherwise be present for shuffling around L3 data, thus allowing greater scalability.

The L1 cache for both types of cores remains the same (L1i$ 32kB, L1D$ 48Kb for P-Cores — L1i$ 64kB, L2D$ 32kB for E-Cores).

A leaked roadmap listed a new feature, a Digital Linear Voltage Regulator (D-LVR), alongside the Raptor Lake chips. According to an Intel patent, this feature helps reduce the CPU VID and power consumed by the cores, possibly reducing power consumption by up to 25% in some cases. Naturally, given that it is in a pitched battle for performance supremacy in the desktop PC space, we would expect Intel to use the headroom afforded from those power savings to deliver yet more effective power to the cores. We aren't sure of this tech's role in the Raptor Lake chips yet, or how effective it will be (if present). We aren't sure if this will be used for the desktop PC or mobile chips, or both, but it could be part of Intel's recipe to improve Raptor Lake's performance-per-watt.

Raptor Lake's E-Cores still do not support AVX-512, so we expect that Intel will keep the feature disabled, which is odd given that AMD's Ryzen 7000 will fully support the extensions. As before, AVX2 and VNNI remain enabled for the E-Cores. We have much more to learn about the Raptor Lake design, but details are still scarce. We'll update this section as we learn more.

INTEL 13TH-GEN ROCKET LAKE 700-SERIES MOTHERBOARDS, Z790, H770, B760, H610


The Raptor Lake chips will use the same LGA1700 socket as Alder Lake, meaning they have the same socket and pinout, and both Raptor and Alder will be compatible with both the 600- and 700-series motherboards, providing quite a bit of flexibility for both generations. However, if you use a Raptor Lake chip on a 600-series motherboard, you'll lose the improvements in PCH PCIe lane configurations that we'll outline below. All LGA1700 coolers are compatible, so you won't need a new CPU cooler for Raptor Lake. Naturally, existing 600-series boards will require an update to support Raptor Lake.

Raptor Lake brings a significant number of big steps forward in connectivity. The previous-gen Alder Lake chips support 16 PCIe 5.0 lanes for a discrete GPU and four PCIe 4.0 lanes from the CPU for an M.2 SSD. Those same lanes are still present on Raptor Lake, but a new connection scheme allows for expanded functionality.

For Raptor Lake, motherboard vendors can now split the 16 PCIe 5.0 PCIe lanes from the CPU into dual x8 arrangements, thus enabling support for PCIe 5.0 M.2 SSDs. This does mean that the connection to the discrete GPU will be split into a x8 connection (a switch could be used here), but the existing PCIe 4.0 link from the CPU for an M.2 SSD will also remain active, providing a total of three M.2 SSD ports that hang directly off the CPU.


Intel itself leaked the 700-series chipset changes. The x8 DMI 4.0 connection between the CPU and the chipset (PCH) remains present, but the chipset also has improvements. In the past, the PCH supported up to 16 PCIe 3.0 lanes and up to 12 PCIe 4.0 lanes, but Intel has increased the number of PCIe 4.0 lanes to 20 and reduced the number of PCIe 3.0 lanes to eight, thus expanding connectivity. Intel also increased the number of USB 3.2 Gen 2x2 (20G) connections from a peak of four to five.


All other PCH connectivity options found with the Alder Lake motherboards remain unchanged with the Raptor Lake chipset itself. However, we will see somewhat different allocations with the Z790, H770, and B760 motherboards based on the new features. You can see Intel's accidentally-released breakdown, which we've independently confirmed, above. The highlighted regions list the changes (Z690 = Z790, H670 = H770, B660 = B760).

INTEL 13TH-GEN ROCKET LAKE GAMING BENCHMARKS AND IPC



Intel demoed Raptor Lake at its Investor Day 2022 using a chip with eight P-Cores and 16 E-Cores, so it was a flagship Core i9 model. The demo of a Blender and After Effects workload didn't give us any performance data to work with. Instead, it merely showed the cores were in good working order and that the chip supports minimizing background tasks to running on the E-Cores only, thus providing more performance for foreground tasks that run on the P-Cores. Aside from the company's vague claims of 'up to double-digit performance boost,' we don't know much about Raptor Lake's performance.

Luckily, we've seen plenty of leaked benchmarks that give us a better idea of what Raptor Lake will look like. Just remember to take these with a grain of salt, as the clock speeds and feature set are not final with the Engineering Samples (ES) chips we've seen in the wild thus far.

The first Raptor Lake benchmark to emerge came from the Crossmark database, but it was later deleted. The benchmark showed 49.3% more performance for a previous-gen chip, indicating this was the rawest of ES silicon. A similarly-unimpressive Raptor Lake benchmark result also appeared in the Ashes of the Singularity benchmark database. Luckily, more expansive benchmarks have emerged since.

We've seen Raptor Lake continue to perform better as new benchmarks are posted, with a 24-core 32-thread Core i9 model showing a 20% improvement in threaded work over the current-gen Core i9-12900K flagship in the UserBenchmark database.


We tend to see early benchmarks emerge in the SiSoft database, but the outfit took that one step further and wrote up a full report on a test submission for the Core i9-13900, showing that the chip boasted up to 33% more performance in integer and 100% more performance in floating-point work than its Alder Lake predecessor. However, in vectorized work, the chip only beat Rocket Lake by 4 to 6%, with the latter holding the lead due to its support for AVX-512.