AMD Naples server processor: More cores, bandwidth, memory than Intel

Two-socket server chip coming in second quarter.

Hot on the heels of the launch of its Ryzen desktop processors last week, AMD today announced the first server chip to be built on the company's new Zen architecture: Naples.

Naples is a two-socket server chip aimed squarely at Intel's Broadwell-EP-based Xeon E5 V4 range, and the overall theme of AMD's chip is "have more of everything." Naples has 32 cores, capable of 64 simultaneous threads, eight memory channels, supporting up to 512GB RAM and 128 PCIe 3.0 lanes. Intel's comparable offering? Twenty-two cores and 44 threads, four memory channels, and a maximum of only 768GB RAM.

In two-socket systems, 64 of the PCIe lanes are used for inter-socket communication. That leaves 64 from each socket available for I/O. The inter-socket communication uses AMD's "Infinity Fabric," the (somewhat ill-defined) high-speed cache coherent interconnect that's also used within Zen. The processor uses the same pins for PCIe as it does Infinity Fabric.

Alternatively, those same I/O channels can be used for direct-attached GPUs (which is to say, not using PCIe). That's comparable to what Nvidia is doing with its NVLink interconnect. Later in the year, AMD is going to ship Radeon Instinct headless GPUs. These will be used for both supercomputing-type workloads as well as accelerated graphics in virtualized desktops. The company is promising that at least four Instinct cards can be used with each Naples processor. The same I/O channels will also support Ethernet and NVMe storage; Naples is, like Ryzen, a system-on-a-chip, and it supports up to 12 NVMe drives. It also supports Ethernet, though AMD hasn't specified the number of Ethernet ports supported or the maximum supported link speed.

The raw numbers certainly favor AMD. The company is also leaning heavily on its pedigree in the server space, pointing out that it was the first to bring out 64-bit x86 processors, the first to integrate the memory controller into an x86 processor, and the first to use a high-speed cache coherent interconnect between its processors. Back when AMD introduced the HyperTransport interconnect, Intel's chips still had their memory controllers on a separate chipset and used the shared front-side bus to connect the chipset to its processors. Simultaneously, AMD is criticizing Intel for its "incremental" approach to its server chips. AMD argues that its larger competitor has failed to equip its processors with the right balance of processing power, memory, and I/O.

However, AMD is not currently offering clock-speed guidance, and the only benchmark it has demonstrated—a floating point-based seismic analysis workload—feels unsatisfactory. AMD compared a dual-socket Naples system against a dual Xeon E5-2699A V4 system. First the company handicapped the Naples machine by limiting it to 44 cores and 1866MHz memory; it ran the sample workload in 18 seconds, compared to Intel's 35 seconds. With the Naples machine using all 64 cores and memory at its maximum speed of 2400MHz, Naples finished the workload in 14 seconds.

These scores strongly suggest that the workload is almost entirely memory bandwidth constrained. At 44 cores and 1866MHz, the Naples machine has twice as much memory bandwidth as the Xeon, thanks to having twice as many memory channels; it also has almost exactly twice the throughput. The full strength (64 cores and 2400MHz) Naples machine shows a 29 percent improvement over the restricted one. The full strength machine also has 29 percent more memory bandwidth and 45 percent more cores. On top of all this, we know that Broadwell's actual floating point performance is, at least when using the AVX instruction set, about twice as much as Zen's at the same clock speed.

Finally, AMD offered a workload that quadrupled the size of the data set. The Naples machine completed the task in 54 seconds, while the Intel system crashed with inadequate memory. This proved convincingly that, yes, 1TB of RAM in one demo system is more than 0.75TB of RAM in the other.

The company promises the chips will ship in the second quarter of this year, at which point we'll also get information on pricing and clock speeds.